Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Transient (SET) immunity. This novel can tolerate particles as charge injection in different internal nodes, well the input output nodes. The of new circuit has been assessed through key parameters, such power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, process variations. A set simulations up to benchmark proposed comparison previous D-latches, Static D-latch, TPDICE-based LSEH-1 DICE D-latches. between these proves that not only better immunity, but features lower PDP, area footprint. Moreover, impact temperature variations, aspect ratio (W/L) threshold voltage transistor variability, on regard D-latches investigated. Specifically, delay PDP improves by 60.3% 3.67%, respectively, when compared reference D-latch. Furthermore, standard deviation variability 3.2%, while its consumption 9.1%. Finally, it shown 56.2%.